Photosensor having gate-all-around structure and method for forming the photosensor

ABSTRACT

A photosensor includes a substrate, a photo-detecting column, a gate structure, a floating node structure and a channel structure. The substrate has a first doping type. The photo-detecting column has a second doping type and is disposed in the substrate. The gate structure is disposed on the substrate in a vertical direction, and is electrically insulated from the photo-detecting column. The floating node structure is disposed on the gate structure opposite to the photo-detecting column in the vertical direction, and is electrically insulated from the gate structure. The channel structure extends through the gate structure, is electrically insulated from the gate structure, and is electrically connected to the photo-detecting column and the floating node structure.

REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. patent applicationSer. No. 17/185,070, filed on Feb. 25, 2021, the content of which isincorporated herein by reference in its entirety.

BACKGROUND

Photosensors, which convert incoming photons into digital signals torealize photosensing, have been widely adopted in various fields ofapplication. There are different structures of photosensors beingproposed for miniaturization or enhancing operation efficiency. Forexample, backside illuminated (BSI) structures have been proposed forimproving the amount of photons received by photosensors. Multiplephotodiodes in a photosensor may share the same transfer gate to achievereduction of device dimension. New structures are still being researchedfor further improving the photosensing performance and dimensionreduction.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a schematic sectional view of a photosensor in accordance withsome embodiments.

FIGS. 2 and 3 are schematic top views showing various arrangements ofmultiple photosensors in accordance with some embodiments.

FIG. 4 is a process flow for making a photosensor in accordance withsome embodiments.

FIGS. 5 through 18 illustrate schematic views of stages in the formationof a photosensor in accordance with some embodiments.

FIG. 19 is a schematic view showing channel regions of a photosensor inaccordance with some embodiments having different structures.

FIG. 20 is a schematic view showing an over-etch of a substrate inmaking a photosensor in accordance with some embodiments.

FIG. 21 is a schematic view showing a gate structure of a photosensor inaccordance with some embodiments.

FIG. 22 is a schematic view showing a floating node structure of aphotosensor in accordance with some embodiments.

FIG. 23 is a schematic top view showing an arrangement of multiplephotosensors in accordance with some embodiments.

FIGS. 24 and 25 are schematic views of photosensors in accordance withsome embodiments.

FIG. 26 through FIG. 28 illustrate schematic views of stages in theformation of a photosensor in accordance with some embodiments.

FIG. 29 through FIG. 32 illustrate schematic views of stages in theformation of a photosensor in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the disclosure.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a schematic sectional view of a photosensor 100 in accordancewith some embodiments. The photosensor 100 includes a substrate 101,which may be a p-type doped semiconductor. The substrate 101 includes ann-type region 106 that is formed in the substrate 101. In someembodiments, the substrate 101 may further include a p-type region 110,which may be referred to as a p-type pinned photodiode (PPPD) region. Insome embodiments, the n-type region 106 includes two deep n-type pinnedphotodiode regions (DNPPD1, DNPPD2) 107, 108 and an n-type pinnedphotodiode (NPPD) region 109. In some embodiments, the n-type region 106and the p-type region 110 may be surrounded by a deep p-well (DPW) 102and a cell p-well (CPW) 103. In some embodiments, a field light dopingregion (FLD) 104 and a shallow trench isolation (STI) 105 may be formedin the cell p-well 103. In some embodiments, an n-type doped region 111may be formed in the substrate 101, and may be referred to as a floatingnode (FD) or a floating diffusion region (FDR). In some embodiments, apixel n-type lightly doped drain (PNLD) 112 may be formed in thesubstrate 101 and extend from the n-type doped region 111. In someembodiments, a gate dielectric layer 113 is formed over the substrate101, and a gate structure 116 is formed over the gate dielectric layer113. In some embodiments, the gate structure 116 may include a gateelectrode 114 and an n-type region 115. The gate electrode 114 may bemade of a suitable material, such as polysilicon or the like. A portionof the gate electrode 114 may be doped to form the n-type region 115. Adielectric layer 117 is conformally disposed on the gate dielectriclayer 113 and the gate structure 116, and may be made from a suitablematerial, such as tetraethyl orthosilicate (TEOS) or the like. A resistprotect oxide (RPO) layer 118 is conformally disposed on the dielectriclayer 117, and may be made of a suitable material, such as silicon oxideor the like. A contact etch stop layer (CESL) 119 is conformallydisposed on the resist protect oxide layer 118, and may be made of asuitable material, such as silicon nitride or the like. An inter-layerdielectric layer (ILD) 120 is disposed over the contact etch stop layer119, and may be made of a suitable material, such as borophosphosilicateglass (BPSG), silicon oxide, fluorine-doped silicon oxide (FSG),carbon-doped silicon oxide, or the like. In some embodiments, thephotosensor 100 may further includes a deep doped region 121 and abackside doping region 122 formed in the substrate 101. In someembodiments, the photosensor 100 may further include an anti-reflectivecoating 123, a color filter film 124 and a microlens 125 connected tothe backside of the substrate 101.

FIG. 2 shows a top view of four photosensors 100 in accordance with someembodiments, in which the schematic sectional view of FIG. 1 is takenfrom line I-I of FIG. 2 . As shown in FIG. 2 , the four photosensors 100share the same n-type doped region 111. Such configuration may bereferred to as a four-share structure, which may be electricallyconnected to various devices, such as a source follower transistor, areset transistor, a row select transistor, or the like, that aredisposed in a region 130 adjacent to the photosensors 100.

FIG. 3 is a top view showing that two photosensors 100 sharing the samen-type doped region 111, in which the schematic sectional view of FIG. 1is taken from line I′-I′ of FIG. 3 . Such configuration may be referredto as a two-share structure, which may be electrically connected to areset transistor 131 and/or a source follower transistor 132.

In accordance with some embodiments, the structure of a photosensor maybe changed from those shown in FIGS. 1 to 3 .

FIG. 4 is a flow chart 200 showing a method of forming a photosensor 300(see FIG. 16 ) in accordance with some embodiments. FIGS. 5 to 16illustrate intermediate steps of forming the photosensor 300. In someembodiments, the photosensor 300 may be a CMOS image sensor (CIS), andin other embodiments, the photosensor 300 may be used for otherphoto-sensing applications.

FIG. 5 is a schematic sectional view showing a substrate 301. Theprovision of the substrate 301 is illustrated as process 202 in the flowchart 200 shown in FIG. 4 . In some embodiments, the substrate 301 maybe a p-type doped silicon substrate, and may have a doping concentrationranging from about 10¹⁵/cm³ to about 10¹⁸/cm³, and other concentrationvalues are also within the scope of the disclosure.

FIG. 5 also shows that the substrate 301 is doped by a suitabletechnique, such as ion implantation or the like. This process isillustrated as process 204 in the flow chart 200 shown in FIG. 4 . Inaccordance with some embodiments, the substrate 301 is doped to form abackside doping region 311. In some embodiments, the backside dopingregion 311 may be p-type doped with a suitable dopant (e.g., boron orthe like), may be referred to as a backside P+ (BS P+) region, and mayhave a doping concentration ranging from about 10¹⁶/cm³ to about10²⁰/cm³, and other concentration values are also within the scope ofthe disclosure. The substrate 301 may be further doped to form a deepdoped region 310 with a suitable dopant, such as arsenic, phosphorus, orthe like. The deep doped region 310 may be referred to as an array deepn-well (ADNW), and may have a doping concentration ranging from about10¹⁶/cm³ to about 10¹⁹/cm³, and other concentration values are alsowithin the scope of the disclosure. The substrate 301 is further dopedto form an n-type doped region 304 (which may be referred to as aphotodiode (PD) region) with a suitable dopant, such as arsenic,phosphorus, or the like. In some embodiments, the n-type doped region304 may have a plurality of sub-regions formed by doping the substrate301 multiple times. In some embodiments, the n-type doped region 304 hasfirst, second and third doped sub-regions 305, 306, 307, which mayrespectively be referred to as a first deep n-type pinned photodiode(DNPPD1) region, a second deep n-type pinned photodiode (DNPPD2) region,and an n-type pinned photodiode (NPPD) region. In some embodiments, eachof the first, second and third doped sub-regions 305, 306, 307 may havea doping concentration ranging from about 10¹⁵/cm³ to about 10¹⁸/cm³,and other concentration values are also within the scope of thedisclosure. In some embodiments, the first, second and third dopedsub-regions 305, 306, 307 may have the same or different horizontalwidths and may have the same or different vertical thicknesses, and then-type doped region 304 may have less than or more than threesub-regions. In some embodiments, the substrate 301 may be further dopedto form a p-type doped region 308 with a suitable dopant, such as boronor the like. In some embodiments, the p-type doped region 308 may belocated above the n-type doped region 304. The p-type doped region 308may be referred to as a p-type pinned photodiode (PPPD) region, and mayhave a doping concentration ranging from about 10¹⁵/cm³ to about10¹⁸/cm³, and other concentration values are also within the scope ofthe disclosure. In some embodiments, the substrate 301 may be furtherdoped, with a suitable dopant (e.g., boron or the like), to form achannel doped region 309, which may be p-type doped and may have adoping concentration ranging from about 10¹⁵/cm³ to about 10¹⁸/cm³, andother concentration values are also within the scope of the disclosure.In some embodiments, the substrate 301 may not be formed with the p-typedoped region 308, and the n-type doped region 304 may be spaced apartfrom the channel doped region 309 or may be adjacent to the channeldoped region 309. In some embodiments, the substrate 301 is furtherdoped, with a suitable dopant (e.g., boron or the like), to form a deepp-well (DPW) 302, which may have a doping concentration ranging fromabout 10¹⁵/cm³ to about 10¹⁸/cm³, and other concentration values arealso within the scope of the disclosure. In some embodiments, the deepp-well 302 may overlap the deep doped region 310. In some embodiments,the substrate 301 is further doped, with a suitable dopant (e.g., boronor the like), to form a cell p-well (CPW) 303, which may have a dopingconcentration ranging from about 10¹⁵/cm³ to about 10¹⁸/cm³, and otherconcentration values are also within the scope of the disclosure. Thedeep p-well 302 and the cell p-well 303 surround the n-type doped region304 and the p-type doped region 308, and may be aligned along a verticaldirection (V). In some embodiments, a horizontal width (W1) of the deepp-well 302 and a horizontal width (W2) of the cell p-well 303 may be thesame; in other embodiments, the horizontal width (W1) of the deep p-well302 and the horizontal width (W2) of the cell p-well 303 may bedifferent. In some embodiments, each of the first, second and thirddoped sub-regions 305, 306, 307 of the n-type doped region 304, and thep-type doped region 308 may be spaced apart from the deep p-well 302and/or the cell p-well 303. In other embodiments, at least one of thep-type doped region 308, the first doped sub-region 305, the seconddoped sub-region 306 and the third doped sub-region 307 may overlap thedeep p-well 302 and/or the cell p-well 303. In some embodiments, thedeep p-well 302 and the cell p-well 303 may be formed before theformation of the n-type doped region 304, the p-type doped region 308and the channel doped region 309.

Referring to FIG. 6 , a mask layer 41 may be formed on the substrate301, and is defined to have a desirable pattern. In some embodiments,the mask layer 41 may be a photoresist layer made of a suitablephotosensitive material. In other embodiments, the mask layer 41 may bea hardmask made of a suitable material, such as metal oxide, metalnitride, or the like, and may be formed by a suitable technique, such asphysical vapor deposition (PVD), chemical vapor deposition (CVD), atomiclayer deposition (ALD), or the like.

Referring to FIG. 7 , after the formation of the mask layer 41, a topportion of the substrate 301 is etched, using the mask layer 41 as anetch mask, to form a channel structure 312. When the channel dopedregion 309 (see FIG. 6 ) is formed, the channel structure 312 is aportion of the channel doped region 309. In some embodiments, thechannel structure 312 may be undoped under the situation that thechannel doped region 309 is not formed, or may be n-type doped. In someembodiments, the channel structure 312 may include one or more channelregion(s) 312′. In some embodiments, each of the channel regions 312′ ofthe channel structure 312 may be a cylinder, which has a rectangularcross section as shown in FIG. 7 . In other embodiments, each of thechannel regions 312′ of the channel structure 312 may be in a shape of afrustum, which has a trapezoid cross section as shown in FIG. 19 , andother shapes are also within the scope of the disclosure. In someembodiments, the etching process may be conducted using a suitableetching technique, such as a fluorine reactive ion etching (RIE), or thelike. Referring to FIG. 20 , in some embodiments, the etching processmay slightly over-etch into the p-type doped region 308 and the cellp-well 303.

Referring to FIG. 8 , after the etching process, the mask layer 41 (seeFIG. 7 ) is removed. The processes illustrated in FIGS. 6 to 8 may becollectively referred to as a process of forming the channel structure,which is illustrated as process 206 in the flow chart 200 shown in FIG.4 . Afterwards, an isolation structure 313 is formed in the cell p-well303. This process is illustrated as process 208 in the flow chart 200shown in FIG. 4 . In some embodiments, the isolation structure 313 maybe made of a suitable material, such as silicon oxide, silicon nitride,silicon carbide or the like, and may be located within the cell p-well303 or may slightly extend outside of the cell p-well 303. In someembodiments, a field light doping region (FLD) 314 may be formed in thecell p-well 303, and may have a doping concentration ranging from about10¹⁷/cm³ to about 10²¹/cm³, and other concentration values are alsowithin the scope of the disclosure. In some embodiments, the isolationstructure 313 may be located within the field light doping region 314.In other embodiments, the isolation structure 313 may be partiallylocated outside of the field light doping region 314.

Referring to FIG. 9 , after the formation of the isolation structure313, a gate dielectric layer 316 is conformally formed on the substrate301 by a suitable technique, such as CVD, PVD, ALD, or the like. Thisprocess is illustrated as process 210 in the flow chart 200 shown inFIG. 4 . In some embodiments, the gate dielectric layer 316 covers a topsurface 340 of the substrate 301 (see FIG. 8 ) and encapsulates thechannel structure 312. The gate dielectric layer 316 may be made of asuitable material, such as silicon oxide, a high-k dielectric material(e.g., hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide,aluminum oxide, zirconium oxide, etc.), or the like. In someembodiments, the gate dielectric layer 316 may have a thickness rangingfrom about 1 nm to about 10 nm. In other embodiments, the gatedielectric layer 316 may have a thickness ranging from about 2 nm toabout 6 nm, and other range values are also within the scope of thedisclosure.

Referring to FIG. 10 , after the formation of the gate dielectric layer316, a gate structure 317 is formed over the substrate 301 by a suitabletechnique, such as CVD, PVD, ALD, or the like. This process isillustrated as process 212 in the flow chart 200 shown in FIG. 4 . Thegate structure 317 may be made of a suitable material, such aspolysilicon, metal or a metal compound (e.g., TiN, TaN, W, Ti, Ta, Al orthe like), or the like. In some embodiments, the gate structure 317 hasa top surface 341 that is lower than a top surface 342 of the channelstructure 312 (see FIG. 8 ), and the gate structure 317 surrounds aportion of the channel structure 312 and a portion of the gatedielectric layer 316 formed on the channel structure 312. In someembodiments, the gate structure 317 may be formed in a controlleddeposition process to have a desirable shape. In other embodiments, thegate structure 317 may be made by covering the gate dielectric layer 316with polysilicon or a metal compound, followed by removing a portion ofthe polysilicon or the metal compound by a suitable etching technique,such as dry etching or the like, to form the desirable shape. Referringto FIG. 21 , in some embodiments, the gate structure 317 may have awider bottom portion and a narrower upper portion, which may be causedby dry etch or the like, and other geometries are also within the scopeof the disclosure.

Referring to FIG. 11 , after the formation of the gate structure 317, asupporting structure 318 is formed over the gate dielectric layer 316and the gate structure 317. This process is illustrated as process 214in the flow chart 200 shown in FIG. 4 . The supporting structure 318 maybe formed by a suitable technique, such as spin-on coating, CVD, ALD orthe like. In some embodiments, a suitable planarization process, such aschemical mechanical planarization (CMP) or the like, may be applied tothe deposited supporting structure 318 to reduce the thickness of thesupporting structure 318 to a desirable amount. In some embodiments, thesupporting structure 318 may be made of a suitable material, such asundoped silicate glass (USG), phosphosilicate glass (PSG), borosilicateglass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-dopedsilicate glass (FSG), silicon dioxide (SiO₂), SiOC-based materials, orthe like. After the formation of the supporting structure 318, a portionof the supporting structure 318 and the gate dielectric layer 316 may beremoved by a suitable technique, such as dry etch, to expose the topsurface 342 of the channel structure 312. Afterwards, in someembodiments, a portion 333 of each of the channel regions 312′ of thechannel structure 312 not surrounded by the gate structure 317 may bedoped with a suitable dopant (e.g., phosphorus, arsenic or the like),and may have a doping concentration ranging from about 10¹⁹/cm³ to about10²¹/cm³, and other concentration values are also within the scope ofthe disclosure. This process is illustrated as process 216 in the flowchart 200 shown in FIG. 4 .

Referring to FIG. 12 , after the doping process, a floating node (FD)structure 319′ (which may also be referred to as a floating diffusionregion (FDR)) is formed over the supporting structure 318, is connectedto the channel structure 312, and is separated from the gate structure317 by the supporting structure 318. This process is illustrated asprocess 218 in the flow chart 200 shown in FIG. 4 . The floating nodestructure 319′ may be formed by a suitable technique, such as CVD, PVD,ALD or the like. The floating node structure 319′ may be made of asuitable material, such as polysilicon, metal or a metal compound (e.g.,TiN, TaN, W, Ti, Ta, Al or the like), or the like. In some embodiments,when the floating node structure 319′ is made of polysilicon, thefloating node structure 319′ may be doped with a suitable dopant (e.g.,arsenic, phosphorus, or the like), and may have a doping concentrationranging from about 10¹⁸/cm³ to about 10²¹/cm³, and other concentrationvalues are also within the scope of the disclosure. In some embodiments,the gate structure 317 and the floating node structure 319′ are made ofthe same material. In other embodiments, the gate structure 317 and thefloating node structure 319′ are made of different materials. In someembodiments, the floating node structure 319′ may be formed by coveringthe supporting structure 318 with a suitable material, followed byetching the suitable material with an appropriate technique (e.g., dryetch or the like) to form the floating node structure 319′ having adesirable shape. Referring to FIG. 22 , in some embodiments, thefloating node structure 319′ may have a wider bottom portion and anarrower upper portion, which may be caused by dry etch or the like, andother geometries are also within the scope of the disclosure.

FIG. 12 also shows that, after the formation of the floating nodestructure 319′, an etch stop layer (ESL) 320 may be formed on thefloating node structure 319′. This process is illustrated as process 220in the flow chart 200 shown in FIG. 4 . The etch stop layer 320 may beformed by a suitable process, such as PVD, CVD, ALD or the like, may bemade of a suitable material, such as silicon nitride (SiN), siliconcarbide (SiC), silicon oxynitride (SiNO), silicon oxide (SiO₂) or thelike, and may have a thickness ranging from about 10 nm to about 200 nm,and other range values are also within the scope of the disclosure.

Referring to FIG. 13 , after the formation of the etch stop layer 320, afirst dielectric layer 321 is formed over the supporting structure 318,the floating node structure 319′ and the etch stop layer 320. Thisprocess is illustrated as process 222 in the flow chart 200 shown inFIG. 4 . The first dielectric layer 321 may be formed by a suitabletechnique, such as spin-on coating, CVD, ALD or the like, and may bemade of a suitable material, such as undoped silicate glass,phosphosilicate glass, borosilicate glass, boron-doped phosphosilicateglass, fluorine-doped silicate glass, silicon dioxide, SiOC-basedmaterials, or the like. In some embodiments, the supporting structure318 and the first dielectric layer 321 are made of the same material. Inother embodiments, the supporting structure 318 and the first dielectriclayer 321 are made of different materials.

Referring to FIG. 14 , after the formation of the first dielectric layer321, a plurality of contact openings 322 are formed to penetrate thefirst dielectric layer 321, the etch stop layer 320 and the supportingstructure 318 such that the floating node structure 319′ and the gatestructure 317 are exposed from the contact openings 322. Each of thecontact openings 322 is defined by an opening wall 332 and is formed bya suitable technique, such as dry etch or the like.

Referring to FIG. 15 , after the formation of the contact openings 322,a contact (CT) structure 323 is formed in the contact openings 322 (seeFIG. 14 ) and is electrically connected to the floating node structure319′ and the gate structure 317. In some embodiments, the contactstructure 323 includes two contacts 323′ that are respectively formed inthe contact openings 322 and are respectively connected to the floatingnode structure 319′ and the gate structure 317. The formation of thecontact openings 322 and the contact structure 323 may be collectivelyreferred to as a step of forming a contact structure, as illustrated asprocess 224 in the flow chart 200 shown in FIG. 4 . The contactstructure 323 may be formed by a suitable technique, such as CVD or thelike, and may be made of a suitable conductive material, such astungsten (W), ruthenium (Ru), cobalt (Co), tantalum (Ta), Titanium (Ti),copper (Cu) or the like. In some embodiments, a suitable planarizationprocess (e.g., CMP or the like) may be adopted to remove an excessamount of conductive material on a top surface 343 of the firstdielectric layer 321. In some embodiments, prior to the formation of thecontact structure 323, the opening wall 332 defining each of the contactopenings 322 (see FIG. 14 ) may be formed with a barrier layer 324. Insome embodiments, the barrier layer 324 may be made of a suitablematerial, such as TaN, TiN, Ru, MnN, ZnO, MoN, Ta, Ti, Co, Ru,combinations thereof, or the like.

Referring to FIG. 16 , after the formation of the contact structure 323,a second dielectric layer 325 may be formed on the first dielectriclayer 321, followed by forming a metal layer 326 in the seconddielectric layer 325 such that the metal layer 326 is electricallyconnected to the contact structure 323, thereby obtaining thephotosensor 300. Such processes are collectively referred to as a stepof forming a metal layer, as illustrated as process 226 in the flowchart 200 shown in FIG. 4 . The metal layer 326 may be formed byemploying a semiconductor back-end process, such as a damascene process,and may be made of a suitable material, such as Cu, Co, W, Ru, Mo, Al orthe like. In accordance with some embodiments, multiple layers ofdielectrics and metal layers may be formed over the first dielectriclayer 321 to form an interconnect structure. In some embodiments, aredistribution layer (RDL) (not shown) may be formed over the metallayer 326.

Referring to FIG. 17 , after obtaining the photosensor 300, the metallayer 326 may be electrically connected to a suitable circuit board 601(e.g., an application specific integrated circuit (ASIC) or the like),followed by thinning the substrate 301 from a backside 327 (see FIG. 16) to a desirable thickness.

Referring to FIG. 18 , after the substrate 301 is thinned, a trenchisolation layer 370 may be formed in the photosensor 300 for providingbetter isolation to the n-type doped region 304 of the photosensor 300.In some embodiments, a trench hole (not shown) may be formed in thebackside 327 (see FIG. 16 ), and may penetrate the backside dopingregion 311 and the deep doped region 310, and reaches the deep p-well302, followed by filling the trench hole with a suitable material, suchas silicon oxide, silicon nitride, silicon carbide or the like.Afterwards, in some embodiments, a backside illumination anti-reflectivecoating (BSI ARC) 328, a color filter (CF) film 329 and a microlens (ML)330 may be sequentially formed on the backside 327 of the substrate 301.

Referring back to FIG. 17 , in some embodiments, a distance (D1) betweenthe gate dielectric layer 316 and the n-type doped region 304 may rangefrom about 1 nm to about 100 nm, and other range values are also withinthe scope of the disclosure. In some embodiments, a minimum distance(D2, D3) between one of the channel regions 312′ and the cell p-well 303may range from about 10 nm to about 500 nm, and other range values arealso within the scope of the disclosure. In some embodiments, D2 may beequal to D3, and in other embodiments, D2 may differ from D3. In someembodiments, a height (D4) of each of the channel regions 312′ of thechannel structure 312 may range from about 10 nm to about 300 nm, andother range values are also within the scope of the disclosure. In someembodiments, a width (D5) of each of the channel regions 312′ of thechannel structure 312 may range from about 1 nm to about 500 nm, andother range values are also within the scope of the disclosure. In someembodiments, the channel region 312′ having the width (D5) less than 1nm may be difficult to make, while the channel region 312′ having thewidth (D5) greater than 500 nm may not be effectively controlled by thegate structure 317. In some embodiments, a distance (D6) between twoadjacent channel regions 312′ of the channel structure 312 may rangefrom about 10 nm to about 1 m, and other range values are also withinthe scope of the disclosure. In some embodiments, a height (D7) of thegate structure 317 may range from about 10 nm to about 300 nm, and otherrange values are also within the scope of the disclosure. In someembodiments, a distance (D8) between the gate structure 317 and thefloating node structure 319′ may range from about 1 nm to about 50 nm,and other range values are also within the scope of the disclosure. Insome embodiments, a width (D9) of the floating node structure 319′ mayrange from about 50 nm to about 1 m, and other range values are alsowithin the scope of the disclosure.

FIG. 23 is a schematic top view showing four photosensors 300, eachhaving a distinct channel structure 312. The channel structure 312 ofthe upper left photosensor 300 includes four of the channel regions312′, each having a circular cross section. The channel structure 312 ofthe upper right photosensor 300 includes only one channel region 312′which has a circular cross section. The channel structure 312 of thelower left photosensor 300 includes two of the channel regions 312′which respectively have a substantially rectangular cross section and anelliptical cross section. The channel structure 312 of the lower rightphotosensor 300 includes three of the channel regions 312′, two of whichhave circular cross sections, and one of which has a substantiallyrectangular cross section. It should be noted that the number, shape,and arrangement of the channel region 312′ of the channel structure 312should not be limited to what are disclosed here, and may be changedaccording to practical requirements. In FIG. 23 , each n-type dopedregion 304 is shown to work with one gate structure 317. However, inother embodiments, there can be multiple n-type doped regions 304sharing one gate structure 317. Multiple pixel devices (not shown),including source follower transistors, reset devices (resettransistors), row select devices (row select transistors) or the like,may be arranged in a region 350 adjacent to the photosensors 300.

Referring to FIG. 24 , in accordance with some embodiments, thephotosensor 300 may include a plurality of gate structures 317 thatrespectively surround the channel regions 312′ of the channel structure312. In some embodiments, one of the channel regions 312′ has arectangular cross section (i.e., is a cylinder), another one of thechannel regions 312′ has a trapezoidal cross section (i.e., is afrustum), and other geometries are also within the scope of thedisclosure.

FIG. 25 shows that, in accordance with some embodiments, two n-typedoped regions 304 are respectively connected to two channel structures312, which are respectively controlled by two gate structures 317. Thechannel structures 312 are both connected to a floating node unit 319which includes one floating node structure 319′. In this embodiments,two contacts 323′ are shown to be connected to the floating nodestructure 319′. The number of the contact(s) 323′ connected to thefloating node structure 319′ can be changed according to practicalrequirements. In other embodiments, the floating node unit 319 mayinclude multiple floating node structures 319′ (only one is shown inFIG. 25 ), and each of the floating node structures 319′ is connected toa respective one of the channel structures 312.

Referring to FIG. 26 , in accordance with some embodiments, after theformation of the isolation structure 313 (i.e., process 208 in the flowchart 200 shown in FIG. 4 ), an opening 315 is formed by a suitabletechnique (e.g., dry etch or the like) to penetrate the p-type dopedregion 308 and the second and third sub-regions 306, 307 of the n-typedoped region 304 and to extend into the first sub-region 305 of then-type doped region 304. In certain embodiments, the opening 315 maystop at the second sub-region 306 or at the third sub-region 307, andmay be defined by an inner wall 360. In some embodiments, the opening315 may have a circular top view (i.e., may be circular when viewingfrom the top), and other geometries are also within the scope of thedisclosure.

Referring to FIG. 27 , after the formation of the opening 315, the gatedielectric layer 316 is conformally formed to cover the inner wall 360(see FIG. 26 ) and the top surface 340 of the substrate 301 (see FIG. 26), and to encapsulate the channel structure 312. The gate dielectriclayer 316 is made by a suitable technique, such as CVD, PVD, ALD, or thelike. The gate dielectric layer 316 may be made of a suitable material,such as silicon oxide, a high-k dielectric material (e.g., hafniumoxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide,zirconium oxide, etc.), or the like. In some embodiments, the gatedielectric layer 316 may have a thickness ranging from about 1 nm toabout 10 nm. In other embodiments, the gate dielectric layer 316 mayhave a thickness ranging from about 2 nm to about 6 nm, and other rangevalues are also within the scope of the disclosure. In some embodiments,the gate dielectric layer 316 in the opening 315 may be thinner thanother portion of the gate dielectric layer 316 (e.g., the gatedielectric layer 316 on the top surface 340 of the substrate 301 (seeFIG. 26 ) and the gate dielectric layer 316 encapsulating the channelstructure 312).

Referring to FIG. 28 , after the formation of the gate dielectric layer316, the gate structure 317 is formed over the substrate 301 by asuitable technique, such as CVD, PVD, ALD, or the like. The gatestructure 317 may be made of a suitable material, such as polysilicon,metal or a metal compound (e.g., TiN, TaN, W, Ti, Ta, Al or the like),or the like. In some embodiments, the opening 315 (see FIG. 27 ) isfilled with the gate structure 317, the gate structure 317 surrounds aportion of the channel structure 312 and a portion of the gatedielectric layer 316 formed on the channel structure 312, and the topsurface 341 of the gate structure 317 is lower than the top surface 342of the channel structure 312 (see FIG. 26 ). The gate structure 317filled in the opening 315 may be referred to as a vertical transfer gate(VTG) 331, which may have a height (D10) ranging from about 100 nm toabout 800 nm, and other range values are also within the scope of thedisclosure. In some embodiments, the vertical transfer gate 331 may beadjacent to one of the channel regions 312′ of the channel structure312. In other embodiments, the vertical transfer gate 331 may be spacedapart from the channel region 312′ by a distance not greater than about200 nm, and other range values are also within the scope of thedisclosure. The number of the vertical transfer gate(s) 331 may be thesame as or different from the number of the channel region(s) 312′ ofthe channel structure 312. After the formation of the gate structure317, processes 214 to 226 in the flow chart 200 shown in FIG. 4 may beconducted.

Referring to FIG. 29 , in the process of doping the substrate 301, thechannel doped region 309 (see FIG. 6 ) may not be formed, and the p-typedoped region 308 and the cell p-well 303 are formed in such a mannerthat top surfaces of the p-type doped region 308 and the cell p-well 303are flush with the top surface 340 of the substrate 301. In otherembodiments, the channel doped region 309 may not be formed, and thep-type doped region 308 is formed in such a manner that the p-type dopedregion 308 is spaced apart from and adjacent to the top surface 340 ofthe substrate 301.

Referring to FIG. 30 , after the doping process, the isolation structure313 and the filed light doping region 314 may be formed in the cellp-well 303.

Referring to FIG. 31 , after the formation of the isolation structure313 and the filed light doping region 314, a mask layer 42 may be formedon the top surface 340 of the substrate 301. In some embodiments, themask layer 42 may be a hardmask made of a suitable material, such asmetal oxide, metal nitride, or the like, and may be formed by a suitabletechnique, such as PVD, CVD, ALD, or the like. Afterwards, the masklayer 42 may be etched by a suitable technique, such as dry etch or thelike, to form one or more openings 421 that expose the top surface 340of the substrate 301.

Referring to FIG. 32 , after the formation and etching of the mask layer42, the channel structure 312 is grown from the top surface 340 of thesubstrate 301 (see FIG. 31 ) by a suitable bottom-up growth technique,such as epitaxial growth or the like. In some embodiments, the masklayer 42 has a thickness ranging from about 1 nm to about 50 nm, andother range values are also within the scope of the disclosure. In someembodiments, after the formation of the channel structure 312, thechannel structure 312 may be doped with a suitable dopant (e.g., boronor the like), and the doping concentration of the channel structure 312may range from about 10¹⁵/cm³ to about 10¹⁸/cm³, and other concentrationvalues are also within the scope of the disclosure. Afterwards, the masklayer 42 may be removed by a suitable technique, such as HF wet etchingor the like. After the removal of the mask layer 42, processes 210 to226 in the flow chart 200 shown in FIG. 4 may be conducted.

The embodiments of the present disclosure have some advantageousfeatures. By having the n-type doped region 304, the channel structure312/the gate structure 317, and the floating node structure 319′ stackedvertically (e.g., along the vertical direction (V) as shown in FIG. 17), the photosensor 300 has a reduced pixel size (i.e., occupies a lessarea). In addition, with the gate structure 317 surrounding the channelstructure 312, the photosensor 300 can have improved switch control.Moreover, the vertical transfer gate 331 improves the pull-outefficiency of the electron from the n-type doped region 304 to thefloating node structure 319′, which, for example, may improve the imagequality (i.e., reduce image lag) of the photosensor 300 when being usedas an image sensor.

In accordance with some embodiments, a photosensor includes a substrate,a photo-detecting column, a gate structure, a floating node structureand a channel structure. The substrate has a first doping type. Thephoto-detecting column has a second doping type and is disposed in thesubstrate. The gate structure is disposed on the substrate in a verticaldirection, and is electrically insulated from the photo-detectingcolumn. The floating node structure is disposed on the gate structureopposite to the photo-detecting column in the vertical direction, and iselectrically insulated from the gate structure. The channel structureextends through the gate structure, is electrically insulated from thegate structure, and is electrically connected to the photo-detectingcolumn and the floating node structure.

In accordance with some embodiments, a photosensor includes a substrate,a plurality of photo-detecting columns, an isolation structure, a gatedielectric layer, a plurality of gate structures, a plurality of channelstructures and a floating node unit. The substrate has a first dopingtype. The photo-detecting columns have a second doping type, and aredisposed in the substrate. The isolation structure is disposed in thesubstrate, and separates the photo-detecting columns from one another.The gate dielectric layer is disposed on the substrate. The gatestructures are disposed on the substrate. Each of the gate structures isaligned with a respective one of the photo-detecting columns and isseparated from the respective one of the photo-detecting columns by thegate dielectric layer. Each of the channel structures is electricallyconnected to a respective one of the photo-detecting columns, penetratesa respective one of the gate structures, and is separated from therespective one of the gate structure by the gate dielectric layer. Thefloating node unit is disposed on the substrate opposite to thephoto-detecting columns, is electrically connected to the channelstructures, and is separated from the gate structures.

In accordance with some embodiments, a method of forming a photosensorincludes: forming an isolation structure in a substrate, the substratehaving a first doping type; forming a photo-detecting column in thesubstrate, the photo-detecting column having a second doping type;forming a channel structure on the substrate, the channel structurebeing electrically connected to the photo-detecting column; forming agate dielectric layer on the substrate, the gate dielectric layerencapsulating the channel structure; forming a gate structure thatsurrounds the channel structure and that is separated from the channelstructure by the gate dielectric layer; forming a supporting structurethat encapsulates the gate dielectric layer and the gate structure;removing a portion of the supporting structure and a portion of the gatedielectric layer to expose a top surface of the channel structure; andforming a floating node structure on the supporting structure, thefloating node structure being connected to the top surface of thechannel structure.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of forming a photosensor comprising:forming a photo-detecting column in a substrate having a first dopingtype, the photo-detecting column having a second doping type opposite tothe first doping type; forming a channel structure over thephoto-detecting column; forming a gate dielectric layer over the channelstructure and the photo-detecting column; forming a gate structure thatsurrounds the channel structure and that is separated from the channelstructure by the gate dielectric layer; forming a supporting structureover the gate dielectric layer and the gate structure; removing aportion of the supporting structure and a portion of the gate dielectriclayer to expose a top surface of the channel structure opposite to thephoto-detecting column; and forming a floating node structure on thesupporting structure in a manner that the floating node structure isdirectly connected to the top surface of the channel structure.
 2. Themethod as claimed in claim 1, wherein forming the channel structureincludes: forming an etch mask on a top portion of the substrate, thetop portion of the substrate being disposed on the photo-detectingcolumn; and etching the top portion of the substrate through the etchmask to form the top portion of the substrate into the channelstructure.
 3. The method as claimed in claim 2, wherein forming thechannel structure further includes doping the top portion of thesubstrate before forming the etch mask.
 4. The method as claimed inclaim 1, wherein forming the channel structure includes: forming apatterned mask layer on the substrate, the patterned mask layer havingan opening that exposes a top surface of the substrate; forming thechannel structure in the opening, the channel structure extending fromthe top surface of the substrate; and removing the patterned mask layer.5. The method as claimed in claim 1, wherein, after removing the portionof the supporting structure and the portion of the gate dielectric layerand before forming the floating node structure, the channel structure isdoped with a dopant having one of the first doping type and the seconddoping type.
 6. The method as claimed in claim 1 further comprising,before forming the gate dielectric layer, forming an opening thatextends into the photo-detecting column, wherein the gate dielectriclayer is formed along an inner surface of the opening and an outersurface of the channel structure to cover the photo-detecting column,and the gate structure is formed around the channel structure and fillsthe opening.
 7. The method as claimed in claim 1, further comprisingforming an isolation structure in the substrate aside thephoto-detecting column.
 8. The method as claimed in claim 1, wherein thegate structure is formed to have a top surface at a level lower that thetop surface of the channel structure.
 9. A method of forming aphotosensor comprising: forming a photo-detecting column in a substratehaving a first doping type, the photo-detecting column having a seconddoping type opposite to the first doping type; forming a gate structureon the photo-detecting column; forming a channel structure penetratingthrough the gate structure in a manner that the channel structure isformed over the photo-detecting column and is insulated from the gatestructure; and forming a floating node structure over the channelstructure in a manner that the floating node structure is directlyconnected to the channel structure and is insulated from the gatestructure.
 10. The method as claimed in claim 9, further comprisingforming a supporting structure between the floating node structure andthe gate structure, such that the floating node structure is insulatedfrom the gate structure through the supporting structure.
 11. The methodas claimed in claim 9, wherein in forming the channel structure, thechannel structure is formed with a portion protruding away from the gatestructure such that a top surface of the gate structure is lower than atop surface of the channel structure, the method further comprising,before forming the floating node structure, doping the portion of thechannel structure with a dopant having one of the first doping type andthe second doping type.
 12. The method as claimed in claim 9, furthercomprising forming a gate dielectric layer between the channel structureand the gate structure, such that the channel structure is insulatedfrom the gate structure through the gate dielectric layer.
 13. Themethod as claimed in claim 9, wherein in forming the channel structure,the channel structure includes a plurality of channel regions, each ofwhich penetrates through the gate structure.
 14. The method as claimedin claim 13, further comprising forming an isolation structure in thesubstrate aside the photo-detecting column.
 15. A method of forming aphotosensor comprising: forming a photo-detecting column in a substratehaving a first doping type, the photo-detecting column having a seconddoping type opposite to the first doping type; forming a channelstructure over the photo-detecting column along a vertical directionforming a gate structure over the photo-detecting column along thevertical direction in a manner that the gate structure is insulated fromthe channel structure, and is formed around a lower portion of thechannel structure; forming a supporting structure over the gatestructure along the vertical direction in a manner that a top surface ofthe channel structure is exposed from the supporting structure; andforming a floating node structure on the supporting structure along thevertical direction in a manner that the floating node structure isdirectly connected to the top surface of the channel structure.
 16. Themethod as claimed in claim 15, further comprising, prior to forming thegate structure, forming an opening in the substrate and penetrating intothe photo-detecting column, in forming the gate structure, the gatestructure being formed around the lower portion of the channel structureand filling the opening in a manner that the gate structure is insulatedfrom the channel structure and the photo-detecting column.
 17. Themethod as claimed in claim 16, further comprising, prior to forming thegate structure and after forming the channel structure and the opening,forming a gate dielectric layer along an inner surface of the openingand an outer surface of the channel structure to cover thephoto-detecting column such that the gate structure is formed to beinsulated from the channel structure and the photo-detecting columnthrough the gate dielectric layer.
 18. The method as claimed in claim15, wherein the photo-detecting column includes multiple regions thatare spaced apart from each other, and the channel structure includesmultiple channel regions that are respectively formed over the multipleregions of the photo-detecting column.
 19. The method as claimed inclaim 18, wherein the floating node structure includes multiple regionsthat are respectively and directly connected to the multiple channelregions of the channel structure.
 20. The method as claimed in claim 18,further comprising forming an isolation structure in the substratebetween two adjacent ones of the multiple regions of the photo-detectingcolumn.